Abstract: Ethernet uplink card is a board in DSLAM equipment with ATM technology as the core. DSLAM equipment can be directly connected to the IP network through it. Because it consumes a lot of resources when converting ATM to IP, it is easy to make The card has become the bottleneck of the entire system. The article proposes a design scheme of Ethernet uplink card based on the network processor IXP1200, which utilizes the powerful data processing capability and high flexibility of the IXP1200 network processor to achieve the wire-speed processing of data, and can also be increased as needed. New features.
With the rapid development of network communication technology, broadband access technology has become a hot spot in current telecommunications access technology. Since the early broadband technology is based on ATM, the core chips and line interface chips provided by major manufacturers are based on ATM technology. The data network mainly takes TCP / IP as the core. Therefore, in order to solve the problem of the integration of ATM and TCP / IP, it is necessary to provide ATM to Ethernet conversion on the DSRAM equipment. However, a large amount of data processing is required during the conversion process, so it is easy to cause system bottlenecks, and the design of the uplink card is to solve the problem of high-speed forwarding between ATM cells and Ethernet frames in the DSLA equipment. This paper presents a design scheme of the UPC card based on the network processor IXP1200, and analyzes the implementation process of the scheme in detail. 
1 Main Features of Network Processor IXP1200
The network processor is a hardware programmable device, usually a chip, which is specifically designed to process network data packets. By optimizing the hardware architecture and instruction set, the network processor can not only provide high-quality hardware functions for processing packets at wire speed, but also have great system flexibility.
IXP1200 is a high-end network processor produced by Intel Corporation, and it is also the core product of IXA (Internet Explorer Arcticure) architecture. The internal structure of IXP1200 is shown in Figure 1. It contains a processing core with a maximum frequency of 232MHz, a STARMARM, 6 programmable micro-engines of RISC structure (each micro-engine contains 4 hardware threads), 64-bit and IX Bus of up to 104MHz, 32-bit SRAM interface unit (operating frequency is half of the core frequency), 64-bit SDRAM interface unit (operating frequency is half of the core frequency), 32-bit and PCI bus interface unit of up to 66MHz, etc. IXP1200 is connected to IX Bus via FBI interface unit. In addition, there is a set of integrated development environment, which can be used for application development of micro-engine, it supports assembly and C programming language.
(1) Stronge ARM Core
The main functions of the CPU can be realized through the STRINGARM Core, and at the same time, it can start the system, manage and control other units of the network processor, process data packets that the micro engine cannot handle, and some abnormal conditions.
(2) Micro engine
The micro engine is a programmable 32-bit RISC processor, and its instruction set is specifically designed for network and communication applications. By programming each thread, the forwarding and processing of the data packet can be performed independently without the intervention of the StrongARM Core, which can reduce the burden of the StrongARM Core, and is particularly suitable for high-speed data processing and forwarding. 
(3) SDRAM unit
The SDRAM unit can provide the interface between IXP1200 and SDRAM, and can support up to 256M bytes of SDRAM. Although the access speed of SDRAM is slow, but the storage space is large, it can be used to store large-capacity data structures (such as data packets and routing tables, etc.), and can store the operating system code while the system is running.
(4) SRAM unit
The SRAM unit can provide a universal bus interface for three types of equipment. These devices include SRAM up to 8M bytes, FLASH or E-PROM where the STROMARM Core executes code after reset, BOOTROM devices and other slow-port devices (such as CAM), encryption devices and the control status of MAC or PHY devices interface. SRAM has a fast access speed, but a small storage space. It is mainly used to store data structures that need to be accessed quickly, such as lookup tables and cache descriptors.
(5) PCI unit
The PCI unit is used to provide an interface to the PCI device and can be used to download operating systems and configuration programs.
(6) FBI unit
The hash unit, IX bus interface, and Snappad memory in Figure 1 are collectively called the FBI unit. IX1200 is connected to IX Bus through FBI unit to realize the sending and receiving of data packets between peripherals and IX1200, so that the micro engine can access these data packets and use threads to forward them. In fact, StrongARM Core can also access these packets and perform exception handling or upper layer protocol handling on them.
2 The design scheme of the uplink card on Ethernet
The basic function of the Ethernet uplink card is to realize the forwarding between ATM cells and Ethernet frames, that is, after receiving the ATM cell flow from the core card from the LVDS interface, it is converted into Ethernet according to the encapsulation protocol (such as RFC 1483 bridge protocol) Frame, and then establish the corresponding relationship between the corresponding MAC address and ATM PVC, and send it to the IP network through the Ethernet uplink port; you can also receive the Ethernet frame from the IP network from the Ethernet uplink port, and then according to the established MAC address and ATM The corresponding relationship of PVC is converted into ATM cell flow, and then sent to the core card through the LVDS interface. 
In the uplink card, the forwarding between ATM cells and Ethernet frames is done by the micro-engine in the network processor. To prevent the Ethernet uplink card from becoming a bottleneck of the network, the micro-engine must be able to process data packets (Ethernet frames or ATM cells) at wire speed, that is, before the arrival of the next data packet, complete the processing of the current data packet. Therefore, the maximum allowable processing time of each data packet should be less than the interval between data packets.
When designing, it should be based on the realization of the specific functions of the card on the Ethernet, and combined with the hardware resources of the network processor IXP1200 to make reasonable allocation and use. This can maximize the performance of the system. In this design, the Ethernet uplink card needs to implement six main tasks: Ethernet receiving processing, CRC calculation generation, ATM sending processing, ATM receiving processing, CRC verification, and Ethernet sending. Because IXP1200 has exactly six micro-engines, it is possible to achieve good results by distributing these six separate tasks on each micro-engine and building it into a multi-pipeline structured program architecture for processing. Figure 2 shows the task distribution scheme of the six microengines of the network processor IXP1200. The entire processing flow of the distribution scheme can be divided into two directions, one is the upstream direction, that is, the data mapping from ATM to Ethernet, and the other is the downstream Direction, that is, data conversion from Ethernet to ATM.
In the upstream direction, the ATM receiving engine assembles the received ATM cells into AAL5 PDUs and converts them into Ethernet frames according to the encapsulation protocol. At the same time, the corresponding relationship between the corresponding MAC address and ATM PVC is established, and then sent to the CRC-32 for verification queue. Next, the CRC-32 check engine performs the CRC check on the PDUs in the queue and sends the PDUs to the Ethernet transmission queue. The task of the Ethernet transmission engine is mainly to send the Ethernet frames in the transmission queue from the Ethernet uplink port.
In the downstream direction, the Ethernet receiving engine receives the Ethernet frame from the uplink port on the Ethernet, encapsulates it into AAL5 PDUs and sends it to the CR-32 generation queue. At the same time, it searches according to the correspondence between the established MAC address and ATM PVC. Get the ATM cell header. Then the CRC-32 generation engine generates the CRC check value for the PDUs in the queue, and sends the PDUs to the UBR queue. Finally, the ATM sending engine splits the PDUs into ATM cells and sends them out from the ATM port.
3. The hardware design of the Ethernet card
Figure 3 shows the hardware circuit of the Ethernet card. The hardware circuit mainly includes four parts: Ethernet processing unit, IXP1200 network processing unit, FPGA control logic unit, ATM and LVDS backplane bus processing unit.
3.1 Ethernet processing unit
The Ethernet processing unit is the uplink processing part of the uplink card and is used to connect data network devices such as routers or layer 3 switches. The unit mainly includes RJ45 interface, transformer isolation circuit, LXT9763 Ethernet physical layer chip and IXF440 MAC layer chip. Among them, RJ45 interface and transformer isolation circuit are standard unit circuits of Ethernet processing interface. LXT9763 mainly completes the physical layer functions described in 802.3 protocol, which is mainly connected to IXF440 chip through MII bus. The IXF440 chip mainly completes the MAC layer function described in the 802.3 protocol, and at the same time provides the IX bus interface with the network processor. In fact, the chip is the SLAVE device of the IX bus in the network processor. 
3.2 IXP1200 network processing unit
The IX1200 network processing unit is the core of the entire Ethernet uplink card. It is mainly connected to the external chip through the IX bus. It is a MAS device of the IX bus. All processing software runs on the network processor.
The IXP1200 network processing unit is composed of a network processor IXP1200 and external chips (such as SDRAM? SRAM? Flash, etc.). SDRAM and SRAM units are intelligent units that can be shared. The SDRAM unit can be directly accessed by the STR1200 ARM core and the micro-engine and PCI bus devices, which can support the rapid movement of data between the SDRAM and the micro-engine or the IX bus and PCI bus, and the SRAM unit has more Fast access time can usually be used to store tables that need to be quickly looked up to improve performance.
3.3 FPGA control logic unit
Because in the network processor solution provided by Intel, the external data interface is the IX bus, which is a proprietary data bus provided by Intel, and the external interface of the ATM chip used in the Ethernet uplink card is standard UTOPIA bus. Therefore, in order to realize the interconnection between the chips, FPGA should be used to complete the transformation between the IX bus and the UTIO bus, that is, the SLAVE interface of the IX bus is implemented on the IX bus side, and the SLAVE interface of the UTOPIA bus is implemented on the ATM side. The FPGA logical control unit can provide the physical layer control function for the conversion of ATM to Ethernet frame. The implementation of FPGA logic control unit is very critical to complete the design of the Ethernet uplink card.
3.4 ATM and LVDS backplane bus unit
The processing unit mainly completes the seamless connection between the network processor unit in the Ethernet uplink card and the backplane ATM. Because the design core of the DSLA equipment is based on ATM technology, in order to apply the network processor unit to the ADSL-based DSLA equipment, the processing unit must be used to implement system interconnection.
The other boards in the DSLA equipment system are mainly used to complete the ATM exchange and the line interface of the ADSL equipment. The backplane is a high-speed differential bus based on the LVDS bus, which has anti-jamming capabilities. This is very important for high-density DSLA equipment. In fact, Shanglian card is interconnected with ATM physical layer chip and high-speed LVDS bus, so that the board can be seamlessly plugged into the system.
4 The software design of the card on the Ethernet
The software of the card on the Ethernet mainly runs in the network processor IXP1200. In order to facilitate the development based on the network processor IXP1200, Intel has launched a highly integrated and powerful development tool SDK2.0. This development kit contains IXP1200 Developer WalkBench, which is an integrated development tool specifically for writing symbol microcode, and has an assembler and optimization equipment. It also provides an IXP1200 simulator that does not require hardware and can support software mode. Under the simulation and debugging, it has a friendly user interface and debugging environment. 
The software development of the network processor IXP1200 is mainly based on two levels, one is high-level software, usually refers to the management software, routing protocol software and all the tasks required by the system running on the network processor IXP1200 Strom Arm, this part of the software usually requires a Embedded operating system, the current development is mainly based on Linux operating system. The other level is the underlying software. This part of the software mainly runs on six micro-engines and can be used to complete the rapid processing of packets, including the rapid forwarding of packets and basic Layer 2 protocol processing. This part of the software uses microcode to Completed, but special attention should be paid to the optimization of the code of the software part, that is, to complete the processing with as few instructions as possible. In the network processor IXP1200, each micro-engine provides 2k words of code storage space. In addition, each microengine also contains four threads, which can constitute hardware multithreading. Because the micro engine contains a large number of GPR and SRAM, SDRAM transfer registers, when using micro threads for relative addressing mode, each thread has its own specific register set, which greatly speeds up the speed of thread switching. There is an important principle for microcode design in IXP1200: that is, when a thread is waiting for resources, it should be switched out to allow other threads to occupy the processing of the micro engine, so that rapid switching can be performed to ensure that each thread can Make full use of the processor of the micro-engine without causing processor waste because of a thread waiting for resources. The organization of microcode is also carried out according to this principle. Figure 4 shows the main flow chart of the high-level software program. The purpose of the high-level software is to complete the initialization of the entire hardware and software, and at the same time load the microcode program into the six microengines of the network processor and start running.
The microcode flow of the underlying software is divided into two parts, and its task allocation is consistent with that of the six microengines discussed above. It is also divided into two directions, namely ATM to Ethernet direction and Ethernet to ATM direction. Figure 5 shows the software flow chart of its microcode.
5 Conclusion
The Ethernet uplink card based on the network processor IXP1200 introduced in this article has been successfully applied to DSLA equipment and solved the problem of high-speed interconnection between the DSLA equipment and the IP network. After testing? The card has good performance and the system runs stably.
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