Since its introduction, the capacity of field-programmable gate arrays (FPGAs) has increased by more than 10,000 times and performance has increased by a factor of 100. The cost and power consumption of unit functions have been reduced by more than 1000 times. These advancements are driven by process scaling techniques, but the story of FPGAs is more complex than simple scaling techniques. The quantitative effect of Moore's Law drives the qualitative changes in FPGA architecture, applications, and methods. Therefore, FPGAs have undergone several different stages of development. This paper summarizes the three stages of invention, expansion and accumulation, and discusses their driving pressure and basic characteristics. The paper concludes with a look at the future of the FPGA phase.
Xilinx introduced the first field-programmable gate arrays (FPGAs) in 1984, although it was not known as FPGAs until Actel became popular in 1988. In the next 30 years, we called FPGA devices. The capacity has increased by more than 10,000 times and the speed has increased by 100 times. The cost and energy consumption per unit of function has been reduced by more than 1000 times (see Figure 1).
Figure 1 Xilinx FPGA properties versus 1988. Capacity refers to the logical cell count. Speed ​​refers to the same functional performance of programmable fabrics. Price refers to each logical unit. Energy refers to each logical unit. The price and energy are amplified by 10,000 times. Source: Data published by Xilinx.
These advances are largely driven by process technology, and with the expansion of semiconductors, it is easy to see the evolution of FPGAs as a simple capacity development. This view is too simple. The true story of FPGA progress is much more interesting.
Since its introduction, FPGA devices have progressed through several different stages of development. Each stage is driven by process technology opportunities and application requirements. These drive pressures cause observable changes in equipment characteristics and tools. In this article, we review the three phases of FPGA. Each phase lasts for 8 years, and each segment is evident in the review.
The three stages are:
1) Invention stage, 1984–1991;
2) Expansion phase, 1992–1999;
3) Accumulation stage, 2000–2007.
Figure 2. FPGA and ASIC intersections. The chart shows the total cost and number of units. The FPGA line is darker, starting from the lower left corner. With the adoption of the next process node (from the dashed arrow of the earlier node to the solid arrow of the later node), the intersection represented by the vertical dashed line becomes larger.
Second, the foreword: What are the major issues concerning FPGA?
A.FPGA VS ASIC
In the 1980s, ASIC companies brought an amazing product to the electronics market: custom integrated circuits. By the mid-1980s, dozens of companies were selling ASICs, and in the fierce competition, low-cost, large-capacity, fast-speed technologies were more popular. When the FPGA appeared, it was not prominent in all of these aspects, but it was unique. Why is that?
The functionality of the ASIC is determined by a custom mask tool. ASIC customers paid for the previous one-time engineering (NRE) fees for these masking tools. With no custom tools, FPGAs reduce the risk of prepaid costs and the creation of custom digital logic. By creating a custom silicon device that can be used by hundreds of customers, FPGA vendors can effectively spread the NRE costs of all customers, so that they don't charge any customers, and at the same time increase each customer. Unit chip cost.
The early NRE costs ensure that FPGAs are more cost effective than ASICs in some quantities. FPGA vendors boast this number on their "intersections", which proves the higher NRE overhead of the ASIC. In Figure 2, the graph shows the total cost of the purchase quantity unit. The ASIC has the initial cost of the NRE, and each subsequent unit increases its unit cost to the total. FPGAs don't have NRE charge, but each unit costs more than a comparable ASIC, so the slope is steeper. The two lines meet at the intersection. If the number of cells required is less than this, the FPGA solution is cheap; exceeding this number of units indicates that the ASIC has a lower overall cost.
Since NRE costs account for a large portion of the total cost of ownership of an ASIC, the advantages of FPGA per unit cost over ASIC cost decrease over time. The dashed line in Figure 2 represents the total cost of a process node. The solid line indicates the case of the next process node, and the NRE cost increases, but the cost per chip is lower. Both FPGAs and ASICs are manufactured at low cost, while ASIC NRE charges continue to climb, pushing the intersection. In the end, the intersection became so high that most customers, the number of units is no longer suitable for ASIC. Custom chips only guarantee very high performance or high volume; all others can use programmable solutions.
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