A few days ago, I saw a person on the Internet saying that in the imitation of the classic basic program button debounce experiment, 0 error, 0 warning, just like I am also copying this experiment, I want to say if I can see such a cool result, I did not expect Finally, there were 6 warnings, so I used the search Dafa and tried to eliminate several warnings! 1.Warning: An incorrect TIme is selected for the Verilog Output (.VO) file of this PLL design. It's required that the TImescale should be 1 ps when simulaTIng a PLL design in a third party EDA tool. This is roughly about time accuracy. In the online check, the precision setting in SETTING was changed from 1ns to the original 1ps, and the warning disappeared. The general meaning of the warning is to simulate the PLL design under the EDA third-party simulation tool, which requires a time precision of 1ps. I don't understand why. This must be done and will be resolved later. 2.Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock for a long time, I thought it was not set the clock pin at the beginning, I still wondered that all the PINs were set, and later I saw that the online clock was not set, so a series of After the setting is finally solved, and understand the clock frequency problem that has not been understood before, the original clock frequency can be set by itself, originally thought it can only be assumed in the testbench, stupid ~ The following is the solution: Select Assignment > Setting Command, fill in the clock frequency in the Classic Timing Analyzer Settings Default required fmax selected under Timing Analysis Settings, click the Indicidual Clocks button below, click New, click the "..." button after the Applies to node, and in the pop-up Node finder Add the corresponding CLK signal to fill the clock settings name (that is, CLK in the program), set the clock frequency and duty cycle, click OK and then go all the way down, then the warning will be lost when compiling 3.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. This is a rather weird warning. I searched the Internet for a long time. There is no exact solution. The general meaning of this information is that the undefined pin is grounded. It doesn't matter, but it doesn't matter whether it affects my 0warning record. So I am at Looking inside, I found out that there is a dialog box device and pin options in the device. After opening, there is an unused pin inside, and the option inside is changed from the original ground to three-state. Then the simulation warning is gone, but the strange thing is Later, I changed it back, and then simulated, the warning still did not appear, somehow. 4.Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF This means that a setting of the clock delay should be set to ON. There is no effect on the Internet. It seems to be related to timing simulation. It is not clear, set in Classic Timing Analyzer. There is a more setting, there is ENABLE_CLOCK_LATENCY in the drop-down menu, set to ON is OK. 5.Warning (10238): Verilog Module Declaration warning at sw_debounce.v(5): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "sw_debounce" This is not found on the Internet, Finally, I had to solve it myself. I simply looked at it. It was roughly a problem with the comma on the port definition. So the mouse climbed over and found that there was a comma after the last port of the defined port. It was sloppy~6.Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. Since the version I use is free, I don't support the logical lock function. I don't know if it affects the program. Go on. Depressed ~~~ did not complete 0warning, but fortunately this is not a technical issue, so I will ignore it for the time being! Solved one night, finally finished the keyboard debounce program!
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