In many bus standards, the slave device must decode all addresses, which is called full address decoding. For example, in the PCI bus, each slave device must have a 32-bit address input, and decode the 32-bit address to determine how to respond to the request of the master device.
On-chip bus specifications such as the Wishbone specification support partial address decoding. In the partial address decoding bus specification, the slave device only needs to decode the address space used by itself. For example, if a slave device has only 4 addresses, it only needs to decode 2-bit addresses instead of 32-bit addresses. The advantage of this is that the address decoding speed is fast, the address decoding logic is less, and the slave device can freely define the width of the address bus.
Figure 26 The realization of Wishbone partial address decoding
The realization of Wishbone partial address decoding is shown in Figure 26. For the IP core shown in the figure, we assume that it has only 4 addresses, corresponding to 4 sets of registers. The address decoder first decodes its address and gives a selection signal, which is in phase with STB_O of the shared bus and STB_I input to the IP core. The lowest 2 bits of the address bus are directly connected to the IP core, and the IP core decodes the specific register selected for the current operation based on these two bits.
The arbiter in the Wishbone shared bus example can be designed as follows:
//theACMP0isforslave0:Flash
//theACMP1isforslave1:SRAM
moduleaddress_decoder2S(addr_i,ACMP0,ACMP1);
input[31:0]addr_i;
outputACMP0,ACMP1;
parameterADDR_LOW_S0=32'b0;
parameterADDR_HIGH_S0=32'h1FFFFF;//2MspaceforSlave0;
//therestofthespaceforSlave1,sowedonotneedadummuyslave;
assignACMP0=addr_i
assignACMP1=~ACMP0;
endmodule
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