We can see a variety of capacitors in the power supply filter circuit, 100uF, 10uF, 100nF, 10nF different capacitance, then how are these parameters determined? Do not tell me to copy other people's schematic diagram, huh, huh. The digital circuit must be stable and reliable, the power supply must be "clean", and energy must be added in a timely manner, that is, the filter decoupling must be better.
What is filter decoupling?
Simply put, the energy is stored when the chip does not need current, and I can add energy in time when you need current. Do not tell me that this responsibility is not DCDC, LDO, yes, they can get at low frequencies, but the high-speed digital system is not the same. First look at the capacitor, the role of the capacitor is simply to store the charge. We all know that we need to add capacitive filtering in the power supply, and place a 0.1uF capacitor decoupling on the power pin of each chip. And so on, how do I see the need for some board chip power capacitor 0.1uF or 0.01uF next to the foot, what is the stress?
To understand this roundabout, we must understand the actual characteristics of the capacitor. The ideal capacitor is just a charge of memory, C. However, the capacitance actually produced is not so simple. When we analyze the integrity of the power supply, we use the capacitance model as shown below.
In the figure, ESR is the series equivalent resistance of the capacitor, ESL is the series equivalent inductance of the capacitor, and C is the real ideal capacitor. ESR and ESL are determined by the manufacturing process and materials of the capacitors and cannot be eliminated. What effect do these two things have on the circuit? ESR affects the ripple of the power supply, and ESL affects the filter frequency characteristics of the capacitor. We know that the capacitive reactance of the capacitor Zc=1/ωC, the inductance of the inductor Zl=ωL, ( ω=2πf), the complex impedance of the actual capacitor is Z=ESR+jωL-1/jωC= ESR+j2πf L-1/j2πf C. It can be seen that when the frequency is very low, the capacitor acts, and when the frequency is high to a certain degree, the effect of the inductor cannot be ignored. When the frequency is high, the inductor plays a leading role. The capacitor loses its filtering effect. So remember that at high frequencies the capacitor is not a simple capacitor. The actual capacitance filter curve is shown in the figure below.
It is said that the equivalent series inductance of the capacitor is determined by the manufacturing process and material of the capacitor. The actual ESL of the chip ceramic capacitor is from a few nH to several nH. The smaller the package is, the smaller the ESL is.
From the filter curve of the above capacitor, we also see that it is not flat, it is like a 'V', that is to say, there is a frequency-selective feature. At the time we want it to be flatter (the previous-stage board-level filtering), And sometimes you want it to be sharper (filtering or notching). The quality factor Q that affects this characteristic is Q, Q=1/ωCESR. The larger the ESR, the smaller the Q and the flatter the curve. Conversely, the smaller the ESR, the larger the Q and the sharper the curve. Usually tantalum capacitors and aluminum electrolysis have a relatively small ESL, and ESR is large, so tantalum capacitors and aluminum electrolysis have a wide range of effective frequencies, which is very suitable for pre-stage board-level filtering.
That is, the DCDC or LDO input stage is often filtered with a larger capacity tantalum capacitor. Some 10uF and 0.1uF capacitors are placed close to the chip to decouple them. Ceramic capacitors have very low ESR. Say so much, then in the end we put 0.1uF or 0.01uF near the pin of the chip, listed below for your reference.
So, don't expect to put 0.1uF capacitors in the future. In some high-speed systems, these 0.1uF capacitors simply don't work.
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