This paper first compares the power consumption of the measured system to verify the accuracy of the FPGA power estimation tool XPower in the Xilinx ISE software package. Then, several interrelated parameters affecting the system power consumption in the FPGA design are sampled, and the system power consumption under different points is estimated by software, the sampling point with the lowest power consumption is found, and the optimal design parameters are obtained, thereby achieving the optimal system design. the goal of. In this experiment, in an FPGA read/write SRAM system, under the condition of fixed read/write operations per unit time, two parameters of read/write frequency and read/write time duty ratio are selected to optimize system power consumption. . The final test data proves the correctness of the method.
FPGAs are widely used in various circuit designs. How to optimize low-power FPGA systems becomes an important practical issue. From the establishment of the earliest FPGA power model [1], to the more complete FPGA power estimation model [2], and now to the emergence of power estimation tools [3], the more the FPGA design has estimated the power consumption. The more accurate, the more energy-efficient methods are available. Based on the estimation of FPGA power consumption, this paper proposes the factor that affects the power consumption as the parameter of the power consumption function. According to the parameter sampling and estimating the power consumption of the sample power, the minimum value of the power function is found, so as to obtain the optimal parameters to optimize the system. A method of designing and conserving system power consumption. A system for reading and writing common memory SRAM is designed. The parameters of read/write frequency and read/write time duty ratio are selected to optimize the system power consumption. The correctness of the method is proved by comparing the estimated value with the measured value.
1 FPGA Power Estimation Tool 1.1 Introduction to XPowerXilinx's ISE Design Suite tool suite provides the power simulator XPower Analyzer, which analyzes the power consumption of programmable logic devices [3]. The power consumption source is divided into two parts: static power consumption and dynamic power consumption [1]. The static power consumption is mainly caused by the leakage current of the transistor and the FPGA bias current. It is related to the process technology, transistor characteristics, the number of transistors, the dielectric used, etc. These are determined by the FPGA itself and are independent of circuit activity. The leakage current of a transistor is mainly composed of three parts: subthreshold leakage current, gate leakage current and source-drain reverse leakage current. The literature has accurately modeled their values ​​[4]. Dynamic power consumption is the energy consumed by the device core or I/O during switching state switching [1].
Dynamic Power is dynamic power; C is capacitance; V is the operating voltage; D is the number of times per node flips per second, and f is the system clock frequency.
XPower creates a capacitance model for each switching component, estimating the power consumption of the FPGA based on the information in the input file and the capacitance of the particular device, static power consumption, and so on. In the input file, the design file NCD (naTIve circuit descripTIon) provides FPGA layout information; the physical constraint file PCF (physical constraint file) provides the design of the clock frequency, operating voltage and other information; user settings file XML is used to save the XPower settings The next time you open the same design, you don't have to repeat these settings; the simulation output file VCD (Value Change Dump) provides the net trough rate, which records the signal changes during the simulation, which can make the power estimation closer to the actual situation [3] ]. NCD files, PCF files, and XML files are generated by the ISE tool after the FPGA logic design code is integrated. The VCD file is generated by ModelSim for timing simulation.
The main output file of XPower is PWR file, which is the power consumption report file. It is divided into static power consumption and dynamic power consumption. It can be seen from the power report files of different logic designs that for the same chip, the static power consumption value is relatively fixed, the logic and operating frequency of the FPGA have less influence on it; the dynamic power consumption and the resources used by the FPGA logic, such as I /O, DCM, DSP module, etc. are also related to the operating frequency and register and line flip rate. The factors that affect both static and dynamic power are voltage and ambient temperature. The closer the parameters that can affect dynamic power are set to the actual situation, the more accurate the XPower estimate will be. Therefore, the parameter setting of XPower is very important, especially the VCD file that determines the rate of network reversal. The simulation situation recorded by it needs to be true and accurate.
The FPGA design flow is shown in Figure 1. It can be seen that XPower estimates the importance of the power consumption. When power consumption is critical, it is often necessary to modify the design file in order to save power.
In order to measure the actual power consumption of the FPGA, a simple system was designed to directly supply the FPGA level with an adjustable DC regulated power supply. Because the system power consumption is small, you need to consider the voltage division loss on the power supply line. You should use a multimeter to measure the voltage as close as possible to the FPGA power supply pin, and adjust the voltage as much as possible to meet the power supply standard selected in the design (VCCO). It is 3.3 V, VCCINT is 1.2 V, and VCCAUX is 2.5 V).
After downloading the configuration file to the FPGA, the actual power consumption of the FPGA is obtained by measuring the current and power supply voltage of the FPGA. Select the corresponding input file of the configuration file in XPower, and make the excitation of the VCD timing simulation file consistent with the actual external excitation, and set the temperature and frequency of XPower to be consistent with the measured condition, and the FPGA can be obtained under the same working conditions. Simulation power consumption.
The FPGA used in this experiment was Xilinx Spartan 3e xc3s100eH with an ambient temperature of 25 °C and a drive clock frequency of 18.432 MHz. Different FPGA logic configuration files are obtained by changing the number of driving clocks of the FPGA logic, the amount of logic used, the number of I/Os, the number of signals, and the like. After actual measurement and XPower estimation, the power consumption measurement data and estimation data under these profiles are obtained respectively. As shown in Figure 2, the abscissa is the FPGA configuration parameter and the ordinate is the power consumption value. From the results, the measured value curve fits well with the estimated value curve.
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