For professional testers, the CP and FT tests are definitely very familiar, but many non-test professionals are not really familiar with these two concepts. So this article will explain the CP and FT tests for those who need to contact the test but not the testers.
According to international practice, we first need to explain what CP and FT test is. CP is an abbreviation of (Chip Probe), which means that the chip is in the wafer stage, and the performance of the chip is performed by the probe pinning on the chip pin. Functional testing, sometimes this process is also called WS (Wafer Sort); FT is the abbreviation of Final Test, which refers to the final test of the chip after the package is completed, only the tested chip will be shipped.
Due to the differences in test fixtures, the differences between CP and FT are not limited to the different process stages. There are obvious differences in efficiency and function coverage. This information is essential for every IC practitioner. of
In most cases, especially in China, the probes we currently use for CP testing are also cantilevered needles (also called epoxy needles, because the needles are fixed with epoxy resin). This type of needle is relatively long and is suspended, and signal integrity is very difficult to control. Therefore, the maximum transmission rate of general data is only 100~400Mbps, and high-speed signal testing is almost impossible; in addition, the probe and the pad are Direct contact is also limited in electrical performance, and it is easy to generate leakage and contact resistance, which will have a huge impact on high-precision signal measurement. Therefore, usually CP testing is only used for basic connection testing and low-speed digital circuit testing.
Of course, in theory, high-speed signals and high-precision signals can be tested in the CP stage, but this often requires the use of professional high-speed probe solutions, such as vertical pin / MEMS probe technology, which will greatly increase the cost of hardware. In most cases, this is not economically viable.
So, do we still need a CP test? Or how to choose a specific test project during the CP test phase? To answer this question, we must have a deep understanding of the purpose of the CP. What is the purpose of the CP?
First of all, the biggest purpose of the CP is to ensure that the bad chips are screened out as much as possible before the chip is packaged to save packaging costs. Therefore, based on this understanding, in the CP test phase, try to select only those test items that have a greater impact on yield. Some test items that are difficult to test, costly, but have a low fail rate can be tested in the FT stage. These projects have little significance in the CP phase and only increase the cost of testing. Be aware that adding a complex high-speed or high-precision simulation test will not only increase the cost of the fixture, but also increase the rate of the test machine and increase the test time. These test items are tested in the FT phase, so there is no need to repeat them in the CP phase.
Secondly, some of the chip's module pins are not introduced when they are packaged, which means that these modules are difficult or impossible to measure in the FT stage. In such cases, the test must be performed during the CP phase. This is also an important reason why CP testing must be performed.
There is also a special case where the package of the chip is a special form such as SIP. On the one hand, this kind of package form has lower measurability in the FT stage, and in the case of multi-chip sealing, the overall yield is greatly affected by the yield of each die, so it is generally necessary to ensure that each die is packaged before packaging. Good product (KGD: Known Good Die). In this case, it is often necessary to test all the test items in the CP stage no matter how difficult.
Therefore, based on the above understanding, it is easier for us to judge the choice of CP test items in specific projects.
In simple terms:
1) Because the package itself may affect the yield and characteristics of the chip, all measurable test items of the chip must be tested in the FT stage. The CP stage is optional
2) The CP phase in principle only measures some basic DC, low-speed digital circuit functions, and other items that are easy to test or must be tested. Any project that can be tested in the FT phase and difficult to test in the CP phase can be tested as much as possible. Some ADC-like tests can only give a few DC levels during the CP phase, confirming that the ADC is working. Reconfirm specific SNR/THD and other indicators in the FT phase
3) Since the test accuracy of the CP stage is often not accurate enough, the test judgment criteria can be appropriately relaxed, and only preliminary screening is performed. Fine and rigorous testing is put into the FT stage
4) If the packaging cost is not large, and the chip itself has a high yield. Can consider not doing CP test, or only do sampling test in CP stage, supervise the process
5) When new products are introduced into mass production, the development nuclear import of the FT test program should be completed first. At the beginning of mass production, FT is far more important than CP. After the products are gradually increased, the CP test can be developed and developed according to the actual situation of the FT.
These are just some of the most basic CP/FT test common sense summarized based on my personal experience. In fact, in a specific project, there will be many complicated problems, and the correspondence and solution of these problems are not covered by a short article. The role of this paper is to provide some of the most basic conceptual information to the majority of non-test professionals. In actual cases, specific analysis of specific issues is often required. All in all, a good test engineer or team is a must for any design company to ensure product yield and cost control.
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