FPGA-based programmable PWM circuit design - Power Circuit - Circuit Diagram

Programmable Package SG-8018CA(SG7050C) 0.67M~170M

MOS power IC full range

Probe current voltage pin 420*4450 head diameter 5.0 over current current and voltage pin

inductance

0 Preface

The H-bridge drive circuit in a system needs to use a Pulse Width Modulation (PWM) signal to drive a motor to control its forward and reverse directions, and the two signals must have a certain time. Intervals to avoid excessive drive current damage to the drive components. In order to make it flexible, for the system requirements, the PWM controller of this design should have the following functions:

(1) There are 3 independent PWM outputs, each output 2 drive signals, and its cycle, duty cycle, dead time should be programmable;

(2) Corresponding to a 10 MHz system clock with a period of 1 μs to 6.5536 ms;

(3) Apply a reduced address line to save the occupation of peripheral pins and address resources;

(4) It can provide bidirectional data interface with 8/16 bits MCU and has built-in address/data latch (74lS373).

1 Structure planning of PWM circuit

In the process of designing a PWM device with a top-down (Top_Down) forward, the structural division and specification customization of the chip are an important part of the overall design, so a reasonable structural design will determine the success or failure of the entire design.

The parameters such as the period, pulse width and dead time of the PWM output signal can be realized by loading the internal registers. The data of the write PWM chip is divided into two parts: data word and control word. The control word information is processed by an internal control logic (ControlLogie) module and decoded to generate an internal information register chip select signal for each internal channel. The data word transmits the characteristic information data of the PWM in each channel module through the internal data bus.

Each module inside the PWM chip can complete data exchange through internal chip selection combined with read and write enable. When the chip exchanges data with the peripheral controller, it can adopt dual mode interface (8/16 bits) and can be selected by external selection pin DataWidth.

The core of the chip is composed of three completely independent and identical channel modules. The data interface inside the channel is used to complete the data transceiving of the external read/write logic (RWLogic) to the internal data bus. The PWM period generation module (ClkGen) can output the PWM period control signal according to the written period information.

The PWM output is completed by the channel state machine. When the channel receives the PWM information data, the data is checked first. The qualified data will start the state machine under the appropriate conditions and complete the PWM output under different conditions. Unqualified data is ignored.

The address/data latch is based on the logic of the general 74LS373 and can be implemented by writing a fully replaceable L74LS373.

According to the above general construction ideas, the overall structure of the final chip is shown in Figure 1.

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