Circuit boards have become an important part of today's electronic products. With the development of electronic technology and printed circuit board manufacturing technology, modern electronic products are becoming more and more complex, and the density of printed circuit boards is increasing, which is followed by printed boards. Testing and repair are also more difficult. In order to improve the automation of the detection and maintenance of printed circuit boards, it is necessary to design an automatic test system for the board.
At present, the automatic test technology of printed circuit boards is developing rapidly. The printed circuit board online test system (ATE) is widely used in the production, inspection and maintenance of printed circuit boards and printed circuit boards of various products. Because the user's test requirements and test objects are different, the specific performance (or function), test principle and test method are also different. It needs to be tailored and customized to meet the requirements of the user, and the system is less versatile. , resource reusability is low. In view of the above situation, this paper designed a more general automatic test system to test whether the circuit board is working properly and realize online testing of various boards.
1 The overall structure of the system
1.1 System overall considerations
The main purpose of this system is to test whether the board is working properly by testing the critical signals on the board. Therefore, the task of the system is to collect the key signals on the circuit board and analyze the results through the software of the PC. The system is divided into three parts: needle bed, signal acquisition and transmission module and test software. As a general-purpose test system, strong versatility was considered in all three parts.
1.2 System Structure
The structural block diagram of this automatic test system is shown in Figure 1. The working principle of the system is: the signal to be tested is derived through the needle bed, the FPGA collects the signal to be tested by controlling the multi-channel analog switch, and the data is transmitted to the PC through the corresponding protocol, and the automatic test software is used to test whether the signals are normal.
Since the frequencies of the signals to be tested differ greatly, there are DC signals, there are also pulse signals with frequencies higher than 103 MHz, and signals with multiple frequencies in between. Therefore, the system uses low-frequency and high-frequency two-group signal sampling circuits to adapt. The need for different signal acquisitions.
1.3 Introduction of the main chip
The main chips used in this system are: main chip EP2S63, AD sampling chip AD7864 and AT84AD331. The following three types of chips are briefly introduced:
The EP2S63 is ALTERA's StraTI family of FPGAs that use the advanced 93 nm manufacturing process; taking FPGA performance to the next level, the industry's fastest and densest FPGA. The EP2S63 has up to 84 dedicated LVDS differential logic receive channels with data transfer rates up to 1 Gb/s per LVDS channel. It has a dedicated high-speed digital phase-locked loop circuit that generates a clock signal that can be used by the ADC circuit.
The AD7864 is a lower speed, low power, 12b A/D converter that can simultaneously sample four channels. It has a 12-bit A/D converter that can simultaneously sample 4 input channels with 4 sample and hold amplifiers; single supply (+5 V), multiple conversion voltage ranges, for each analog input channel Overvoltage protection circuit; when the 4 channels are working simultaneously, the maximum sampling rate is 133 kHz.
The AT84AD331 is a high-speed acquisition chip from Atmel. The device integrates two (I and Q) independent ADCs with 8 b conversion accuracy, with a sampling rate of 1 Gs/s per channel and 2 Gs/s in interleaved mode. The chip is based on the requirements of high-speed applications, analog input, digital clock input, digital clock output, data output, and synchronous clock output are all differential. The data output adopts the LVDS standard, and its transmission rate can reach 1 Gb/s. With its internal demultiplexer, the output data rate can be reduced, and it can be easily connected directly to many types of high-speed FPGAs.
With the 1:2 mode, the output data rate is reduced to 533 Mb/s, which is sufficient for most FPGAs to receive data.
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