PCI-X
The PCI-X bus developed on the basis of the PCI bus, which is compatible with the PCI bus at the software and hardware level, but it has significantly improved the performance of the bus. In other words, the PCI-X device can be directly inserted into the PCI slot, and the PCI device can also be plugged directly into the PCI-X slot.
From a hardware perspective, PCI-X inherits Reflected-Wave Signaling from the PCI bus, but adds input registers at the input of the signal to enhance timing performance and increase the bus clock frequency. DDR and QDR technologies have also been proposed in the Spec for PCI-X2.0, which further increases the bandwidth of the PCI-X bus.
An example of a typical PCI-X bus system is shown below:
The following is an example of a PCI-X Burst Memory Read Bus Cycle:
In the PCI bus, taking the bus master reading from the slave device as an example, when the slave device is not ready to end this operation (the slave device is not ready and the data has not been sent yet), the data can be latched and inserted. Wait for a period, or initiate a Retry operation. The PCI-X bus uses a method called Split Transaction to handle this situation, as shown in the following figure. At this point, the bus master that initiated the read operation is called the Requester, and the slave device that receives and sends data to the bus is called the Completer.
Note: PCIe Spec inherits the naming convention of PCI-X.
The bus transfer utilization (efficiency) of the PCI-X bus in this way can reach 85%, while the standard PCI bus is only 50%-60%. Regarding the details of Split Transaction, it is recommended that you refer to PCI-X Spec, which is not described in detail here. In addition, the PCI-X bus also includes NS (No Snoop) and RO (Relaxed Ordering) bits in the Configuration Address Register to improve bus transfer efficiency.
As mentioned in the previous article, the PCI bus interrupt operation is performed through a series of Sideband Signals. In PCI-X Spce, the mechanism of Message Signaled Interrupts (MSI) is introduced. Instead of these sideband signals, the system design can be streamlined.
Note: For the details of MSI, it is recommended to refer to PCI-X Spec, which is not described in detail here.
Before introducing the source synchronization model proposed in PCI-X 2.0, let's first talk about the internal problems of the non-source synchronization model. The so-called non-source synchronization, that is, the signal sender and receiver of the clock are driven by one or two clock sources, the sender and receiver of the same frequency clock, but it is difficult to ensure the same phase (that is, there is the clock phase deviation Skew).
As shown in the above figure, due to the large number of signal lines, it is difficult to ensure that the length of each signal line is exactly the same in the PCB design (not to mention factors such as vias). Therefore, even if the signal is completely along the opposite edge (which is practically impossible, for the PCI bus) when transmitting, it is difficult to ensure that the signal arrives at the receiving end at the same time. At this time, the signal is no longer along the edge. It's up. If the transmission delay between different signal lines differs greatly, it is very easy to cause the sampling error of the signal at the receiving end, thereby improving the bit error rate of the data transmission.
In order to solve these problems, the source synchronization model was proposed in the spec of PCI-X2.0 (in fact, the source synchronous models are basically used in the current high-speed FPGA logic design and digital ASIC design). As shown in the figure below, the clock of the system is directly provided by the sending end (Source Device) and transmitted to the receiving end together with the data signal. This well solves the clock skew (skew) in the non-source synchronization model. problem. In addition, PCI-X2.0 also supports DDR input and even QDR input on the basis of receiver input registers, which greatly increases the bus bandwidth. The bandwidth of the 64-bit 133MHz PCI-X2.0 QDR bus has even reached a staggering 4262MB/s! It is basically the peak of a parallel bus (DDR SDRAM is not a bus).
However, it is interesting that PCI-X 2.0 seems to be out of date. Although it significantly increases the bandwidth of the PCI bus, it still cannot hide the disadvantage of the parallel bus in high-speed bus data transmission. Although the PCI-X2.0 bus has excellent performance, it is rarely used. Due to its high power consumption and high cost, and the parallel bus has too many pins, it requires extremely complex PCB design, resulting in PCI-X2.0 only Very few high-end markets have been used (such as the server market, etc.). Another factor that has caused PCI-X2.0 to fail to reach large-scale applications is the advent of the PCI Express (PCIe) bus era, which marked the beginning of the era of high-speed serial buses replacing traditional parallel buses.
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