The biggest advancement of CPLD over older PLD devices is that it can accommodate a large amount of logic in a single device. In theory, you can continue to add LAB to the CPLD and continue to increase the number of logic. However, doing so requires additional PI routing to achieve the connection of all of these LABs, and the number of connections will increase exponentially until the number of connections to the chip die exceeds the logical number, which limits the expansion of capacity.
The solution is to arrange the LABs in a grid, resulting in the concept of a field programmable gate array FPGA. The LABs are arranged in a large array, and the devices can be programmed or reprogrammed in the field, just like CPLDs. Instead of using a central global device interconnect, the wiring is placed in a space between the LABs, just like the streets of a big city. Such wiring is arranged in the form of row and column interconnections. It can span the entire length and width of the device, or a small portion of the device, covering only a few LABs in the row, as shown in Figure 1.9.
Figure 1.9 FPGA Interconnect Diagram
The LAB design of FPGA LAB and CPLD is different. CPLD LAB consists of macrocells, including its own local programmable array, while FPGA LABs consist of a large number of logic blocks called LEs, which are separated by local interconnects and logic. LEs may look similar to CPLD macrocells, but are easier to configure and have richer features to improve performance and reduce wasted logic resources.
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